In digital data transmission and storage systems, digital data becomes converted into an analog signal representation incident to being sent through an analog transmission medium, such as the airwaves in the case of radio frequency communications, or a magnetic storage medium in the case of magnetic storage systems, for example. At the receiving end, the received analog signal typically must undergo some form of analog signal processing, such as amplification, and wave shaping or equalization, to facilitate the digital data recovery process.
It is typically during this signal conditioning process at the receiving end that direct current (DC) offset is introduced into the received analog signal. DC offset may be caused by the fact that analog signal processing circuitry, such as amplifiers, and filters, for example, are not ideal devices, and have an inherent amount of DC offset associated with their response characteristics. Further, the DC offset of these devices is usually not uniform, and varies as a function of temperature, integrated circuit process, signal gain, etc. The DC offset associated with these non-ideal devices manifests itself as a shift in the signal level of the analog waveform which, when uncorrected, can degrade the performance of the digital data recovery process.
In disk drive storage systems it has been conventional to use continuous time, analog peak detection schemes to recover digital data written as a series of magnetic transitions on a recording surface of a rotating magnetic disk. Recently, sampled data detection techniques such as Partial Response ("PR") signalling and Maximum Likelihood ("ML") sequence detection (collectively "PRML") have been employed in magnetic recording systems. An example of a PRML data channel architecture is illustrated in commonly assigned, U.S. patent application Ser. No. 07/937,064.
Typical PRML data channels have ML detectors that determine the data based on an analysis of samples taken from the received analog waveform, rather than just one peak point as is the case with peak detection techniques. In a sampled data system using a PRML channel, the incoming analog waveform is sampled and quantized using an analog to digital ("A/D") converter at predetermined proper sampling times. Thus, the clock to the A/D converter is synchronized and phase aligned to the incoming data to sample at the proper time. To this end, PRML channels typically employ a timing loop to rapidly acquire frequency and phase synchronization of the A/D converter clock with the incoming data stream. An example of an improved timing loop in a disk drive application, particularly a multi-mode analog and digital timing loop is disclosed in U.S. application Ser. No. 07/937,064. Another exemplary multi-mode timing loop is also disclosed in commonly assigned U.S. Pat. No. 5,258,933 to Johnson et al., the disclosure of which is also hereby incorporated by reference in its entirety as if fully set forth herein.
Another control loop typically utilized in the analog signal conditioning process in a PRML channel is a gain control loop. The gain control loop is used to adjust the signal amplitude of the analog data stream presented to the input of the A/D converter so as to achieve full utilization of the converter's dynamic range. An example of a rapidly acting analog and digital multi-mode gain control loop is disclosed in U.S. application Ser. No. 07/937,064.
Shifts in the incoming analog signal level attributable to DC offset may affect the acquisition of the gain and timing control loops, resulting in a degradation of the quality of the channel. Another problem typically caused by DC offset is the effect it has on the gain control loop with regard to the reduction of the overall A/D converter range which can lead to signal saturation.
One known approach for cancelling DC offset is to use AC coupling between the analog circuit elements introducing DC offset and the remainder of the read channel. This technique involves employing DC blocking capacitors after the analog circuit elements introducing DC offset and thereby removing any DC component present in the analog signal. However, this approach can slow control loop response, and result in the undesirable effect of reducing signal bandwidth at low frequencies.
Another known approach for cancelling DC offset is a non-real time approach wherein the DC offset of the received analog signal is measured once during channel initialization, for example, and a correction value is applied to the channel during data reception operations based on this initial measurement. The measured correction value is typically held until the channel is re-initialized. This approach is likewise not optimal as it makes initialization time longer, and increases the drive's Random Access Memory ("RAM") requirements. Most importantly, this system does not function in real-time in that dynamic changes in DC offset occurring during data reception operations are not taken into account and therefore are not compensated for.
A variation on this latter approach, in which it is suggested that a circuit should be employed in a disk drive to remove DC offset during disk drive idle times (i.e., when the disk drive is not servicing a user request for reading or writing data), appears in an article by Schmerbeck et al., entitled, "A 27 MHz Mixed Analog/Digital Magnetic Recording Channel DSP Using Partial Response Signalling with Maximum Likelihood Detection," Paper TP 8.3, IEEE International Solid State Circuits Conference, 1991. This circuit would also not function in real-time.
A third known approach is continuous DC offset control. This approach is suboptimal since it operates continuously over the analog data stream, in the process changing the data's signal shape characteristics and introducing loop noise which degrades the signal to noise ratio of the channel. In order to compensate for the signal shape distortion to the data signal it is necessary to add a correcting block to the channel, thereby increasing system complexity, and power consumption. Additionally, it is typically not necessary to track DC offset values over the data because of the relatively slow changes in DC offset that occur over the length of a typical data sector.
Accordingly, it would be desirable to have a simple DC offset cancellation control loop that functions in real-time during data reception operations without operating over the received user data field. Another desirable aspect of such a system would be to cancel DC offset without affecting the operation of the other signal processing control loops.